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dual-channel ultralow noise amplifier with selectable gain and input impedance AD8432 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009 analog devices, inc. all rights reserved. features low noise input voltage noise: 0.85 nv/hz current noise: 2.0 pa/hz excellent ac specifications 200 mhz bandwidth (g = 12.04 db) 295 v/s slew rate selectable gain g = 12.04 db (4) g = 18.06 db (8) g = 21.58 db (12) g = 24.08 db (16) active input impedance matching integrated input clamp diodes single-ended input, differential output supply range: 4.5 v to 5.5 v low power: 60 mw/channel applications cw doppler ultrasound front ends low noise preamplification predriver for i/q demodulators and phase shifters wideband analog-to-digital drivers functional block diagram bias enb comm inh1 ind1 inl1 inh2 ind2 inl2 v ps1 v ps2 oph1 opl1 gmh1 goh1 gol1 gml1 oph2 opl2 gmh2 goh2 gol2 gml2 lna1 lna2 AD8432 08341-001 figure 1. general description the AD8432 is a dual-channel, low power, ultralow noise amplifier with selectable gain and active impedance matching. each amplifier has a single-ended input, differential output, and integrated input clamps. by pin strapping the gain setting pins, four accurate gains of g = 12.04 db, 18.06 db, 21.58 db, and 24.08 db (4, 8, 12, and 16) are possible. a bandwidth of 200 mhz at g = 12.04 db makes this amplifier well suited for many high speed applications. the exceptional noise performance of the AD8432 is made possible by the active impedance matching. using a feedback network, the input impedance of the amplifiers can be adjusted to match the signal source impedance without compromising the noise performance. impedance matching and low noise of the AD8432 allow designers to create wider dynamic range systems that are able to detect even very low level signals. the AD8432 achieves 0.85 nv/hz input referred voltage noise for a gain of 12.04 db. the AD8432s ultralow noise, low distortion, excellent gain accuracy, and channel-to-channel matching are ideal for high performance ultrasound systems and for processing i/q demodulator signals. the AD8432 operates on a single supply of 5 v at 24 ma. it is available in a 4 mm 4 mm, 24-lead lfscp. the lfcsp features an exposed paddle that provides a low thermal resistance path to the pcb, which enables more efficient heat transfer and increases reliability. the operating temperature range is ?40c to +85c.
AD8432 rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? absolute maximum ratings ............................................................ 5 ? thermal resistance ...................................................................... 5 ? maximum power dissipation ..................................................... 5 ? esd caution .................................................................................. 5 ? pin configuration and function descriptions ............................. 6 ? typical performance characteristics ............................................. 7 ? test circuits ..................................................................................... 16 ? theory of operation ...................................................................... 18 ? low noise amplifier (lna) ..................................................... 18 ? gain setting technique ............................................................. 18 ? active input resistance matching ............................................ 19 ? applications information .............................................................. 21 ? typical setup ............................................................................... 21 ? i/q demodulation front end ................................................... 23 ? differential-to-single-ended conversion ............................... 24 ? evaluation board ............................................................................ 25 ? gain setting ................................................................................. 25 ? power supply ............................................................................... 27 ? input termination ...................................................................... 27 ? output .......................................................................................... 27 ? outline dimensions ....................................................................... 28 ? ordering guide .......................................................................... 28 ? revision history 10/09revision 0: initial version
AD8432 rev. 0 | page 3 of 28 specifications v s = 5 v, t a = 25c, r s = r in = 50 , r fb =150 , c sh = 47 pf, r sh = 15 , r l = 500 (per se output), c l = 5 pf (per se output), g = 12.04 db (single-ended input to differential output), f = 1 mhz, unless otherwise specified. table 1. parameter conditions min typ max unit dynamic performance gain range input to differential o utput (selectable gain) 12.04 24.08 db input to single output (sel ectable gain) 6.02 18.06 db gain error 0.1 1 db ?3 db small signal bandwidth r in unterminated, r fb = , c sh = 0 pf, r sh = 0 g = 12.04 db 200 mhz g = 18.06 db 90 mhz g = 21.58 db 50 mhz g = 24.08 db 32 mhz ?3 db large signal bandwidth v out = 2 v p-p 42 mhz slew rate (rising edge) v out = 2 v p-p, f = 10 mhz 295 v/s slew rate (falling edge) v out = 2 v p-p, f = 10 mhz 170 v/s overdrive recovery time 10 ns distortion/noise performance input voltage noise r fb = 0.85 nv/hz input current noise r fb = 2.0 pa/hz noise figure unterminated r s = 50 , r fb = 2.8 db active termination r s = r in = 50 , r fb = 150 4.8 db r s = 50 , r fb = 226 , r in = 75 4.2 db r s = 50 , r fb = 301 , r in = 100 3.2 db r s = 50 , r fb = 619 , r in = 200 2.1 db r s = 50 , r fb = 3.57 k, r in = 1 k 2.3 db output referred noise g = 12.04 db, r fb = 3.4 nv/hz g = 18.06 db, r fb = 6.8 nv/hz g = 21.58 db, r fb = 10.2 nv/hz g = 24.08 db, r fb = 13.6 nv/hz harmonic distortion 1 mhz (v out = 1 v p-p) hd2 ?67 dbc hd2, r s = 50 , r in unterminated ?74 dbc hd3 ?103 dbc hd3, r s = 50 , r in unterminated ?106 dbc 1 mhz (v out = 2 v p-p) hd2 ?65 dbc hd2, r s = 50 , r in unterminated ?72 dbc hd3 ?103 dbc hd3, r s = 50 , r in unterminated ?92 dbc 10 mhz (v out = 1 v p-p) hd2 ?66 dbc hd2, r s = 50 , r in unterminated ?62 dbc hd3 ?78 dbc hd3, r s = 50 , r in unterminated ?73 dbc 10 mhz (v out = 2 v p-p) hd2 ?60 dbc hd2, r s = 50 , r in unterminated ?56 dbc hd3 ?72 dbc hd3, r s = 50 , r in unterminated ?65 dbc
AD8432 rev. 0 | page 4 of 28 parameter conditions min typ max unit two-tone imd3 distortion r s = 50 , r in unterminated 10 mhz v out = 1 v p-p, f1 = 9.5 mhz, f2 = 10.5 mhz ?89.1 dbc v out = 2 v p-p, f1 = 9.5 mhz, f2 = 10.5 mhz ?66.0 dbc 1 mhz v out = 1 v p-p, f1 = 0.9 mhz, f2 = 1.1 mhz ?88.9 dbc v out = 2 v p-p, f1 = 0.9 mhz, f2 = 1.1 mhz ?73.7 dbc input 1db compression point f = 1 mhz 7.5 dbm f = 10 mhz 7.7 dbm output third-order intercept 1 mhz v out = 1 v p-p of composite tones 29.7 dbv rms v out = 2 v p-p of composite tones 28.2 dbv rms 10 mhz v out = 1 v p-p of composite tones 23.2 dbv rms v out = 2 v p-p of composite tones 24.2 dbv rms 1 mhz v out = 1 v p-p of composite tones, reference to 50 42.7 dbm v out = 2 v p-p of composite tones, reference to 50 41.2 dbm 10 mhz v out = 1 v p-p of composite tones, reference to 50 36.2 dbm v out = 2 v p-p of composite tones, reference to 50 37.2 dbm crosstalk v out = 1 v p-p, f = 1 mhz 102 db dc performance input offset voltage ?6.25 +1 +6.25 mv input offset voltage drift 300 v/c input characteristics input voltage range ac-coupled 1.2 v p-p input resistance r fb = 150 50 r fb = 226 75 r fb = 301 100 r fb = 619 200 r fb = 3.57 k 1 k r fb = , f = 100 khz 6.2 k input capacitance 6 pf input common mode voltage 3.25 v output characteristcs output common-mode voltage 2.5 v output offset voltage ?25 +4 +25 mv output voltage swing 4.8 v p-p output resistance single-ended, either output <0.1 output resistance in shutdown mode single-ended, either output 2.5 k output short-circuit current r l = 10 differential 77 ma enable response time enb on (enable high to output on) 200 s enb off (enable low to output off ) 200 s power supply supply voltage 4.5 5 5.5 v quiescent current all channels enabled 24 ma over temperature t a = ?40c 21 ma t a = +85c 27 ma supply current in shutdown mode enb = gnd 50 100 a power dissipation 120 mw psrr g = 24.08 db, f = 100 khz, no bypass capacitors ?82 db
AD8432 rev. 0 | page 5 of 28 absolute maximum ratings maximum power dissipation table 2. parameter rating voltage supply voltage 5.5 v input voltage 0 v to vps power dissipation 120 mw temperature operating temperature C40c to +85c storage temperature C65c to +150c package glass transition temperature (t g ) 150c lead temperature (soldering, 60 sec) 300c the maximum safe power dissipation for the AD8432 is limited by the associated rise in junction temperature (t j ) on the die. at approximately 150c, which is the glass transition temperature, the properties of the plastic change. even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the amplifiers. exceeding a temperature of 150c for an extended period can cause changes in silicon devices, potentially resulting in a loss of functionality. esd caution stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. the ja values in tabl e 3 assume a 4-layer jedec standard board with zero airflow. table 3. thermal resistance 1 parameter ja jc jb jt unit 40-lead lfcsp 57.9 11.2 35.9 1.1 c/w 1 4-layer jedec board (2s2p).
AD8432 rev. 0 | page 6 of 28 pin configuration and fu nction descriptions 08341-002 2 1 3 4 5 6 18 17 16 15 14 13 inh2 inl2 c omm ind1 inl1 inh1 gol 2 o pl2 com2 com1 opl1 gol1 8 9 10 11 7 vps2 oph2 goh2 g mh2 12 gml2 ind2 20 19 21 gmh1 gml1 g oh1 22 oph1 23 vps1 24 enb AD8432 top view (not to scale) notes 1. exposed pad must be connected to ground. figure 2. pin configuration table 4. pin function descriptions pin no. nemonic description 1 inh1 lna1 noninverting input. 2 inl1 lna1 inverting input (ac-coupled to ground). 3, 7 ind1, ind2 integrated input clamping back-to-back diodes. 4 comm input ground. 5 inl2 lna2 inverting input (ac-coupled to ground). 6 inh2 lna2 noninverting input. 8 vps2 5 v supply for lna2. 9 oph2 noninverting output of lna2. 10 goh2 gain setting pin for lna2. 11 gmh2 gain setting pin for lna2. 12 gml2 gain setting pin for lna2. 13 gol2 gain setting pin for lna2. 14 opl2 inverting output of lna2. 15 com2 lna2 output ground. 16 com1 lna1 output ground. 17 opl1 inverting output of lna1. 18 gol1 gain setting pin for lna1. 19 gml1 gain setting pin for lna1. 20 gmh1 gain setting pin for lna1. 21 goh1 gain setting pin for lna1. 22 oph1 noninverting output of lna1. 23 vps1 5 v supply of lna1 . 24 enb enable. epad exposed pad must be connected to ground.
AD8432 rev. 0 | page 7 of 28 typical performance characteristics v s = 5 v, t a = 25c, r s = r in = 50 , r fb =150 , c sh = 47 pf, r sh = 15 , r l =500 (per se output), c l = 5 pf (per se output), g = 12.04 db (single-ended input to differential output), f = 1 mhz, unless otherwise specified. 08341-003 ?30 ?24 ?12 0 12 6 ?6 18 ?18 30 24 1 10 100 1k gain (db) frequency (mhz) g = 24.08db g = 21.58db g = 18.06db g = 12.04db figure 3. small signal differential gain vs. frequency, r in unterminated ?12 ?9 ?6 ?3 0 12 24 1 10 100 500 gain (db) frequency (mhz) r in unterminated r in = 200 ? r in = 100 ? r in = 50 ? 08341-004 3 6 9 15 18 21 figure 4. small signal frequency response vs. r in , g = 12.04 db 0 3 6 9 15 18 21 12 24 1 10 100 500 gain (db) frequency (mhz) r in unterminated r in = 200 ? r in = 100 ? r in = 50 ? 08341-005 figure 5. small signal frequency response vs. r in , g = 18.06 db 0 24 1 10 100 500 gain (db) frequency (mhz) r in unterminated r in = 200 ? r in = 100 ? r in = 50 ? 08341-006 3 6 9 15 18 12 figure 6. small signal frequency response vs. r in , g = 21.58 db 0 24 27 1 10 100 500 gain (db) frequency (mhz) r in unterminated r in = 200 ? r in = 100 ? r in = 50 ? 08341-007 3 6 9 15 18 21 12 figure 7. small signal frequency response vs. r in , g = 24.08 db 1 10 100 500 gain (db) frequency (mhz) 0 8341-010 0 ?3 ?6 ?9 24 27 3 6 9 15 18 21 12 g = 12.04db g = 18.06db g = 21.58db g = 24.08db figure 8. differential gain vs. frequency, v out = 1 v p-p, r in = 50
AD8432 rev. 0 | page 8 of 28 ?24 ?12 ?6 ?18 0 12 30 24 18 6 1 10 100 1k gain (db) frequency (mhz) 08341-011 g = 24.08db g = 21.58db g = 18.06db g = 12.04db figure 9. differential gain vs. frequency, v out = 2 v p-p , r in = 50 45 46 47 48 49 51 52 53 54 50 55 0.1 1 10 frequency (mhz) input impedance ( ? ) g = 24.08db g = 21.58db g = 18.06db g = 12.04db 08341-029 figure 10. input impedance r in vs. frequency, 50 active termination 85 90 95 100 105 110 115 0.1 1 10 input impedance ( ? ) frequency (mhz) g = 24.08db g = 21.58db g = 18.06db g = 12.04db 08341-030 figure 11. input impedance r in vs. frequency, 100 active termination 0.1 1 10 frequency (mhz) 160 170 180 190 200 210 220 230 240 g = 24.08db g = 21.58db g = 18.06db g = 12.04db input impedance ( ? ) 08341-031 figure 12. input impedance r in vs. frequency, 200 active termination 0.1 1 10 frequency (mhz) 0.1 1 10 input impedance (k ? ) g = 24.08db g = 21.58db g = 18.06db g = 12.04db 0 8341-032 figure 13. input impedance r in vs. frequency, unterminated 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.1 1 10 100 output impedance ( ? ) frequency (mhz) 08341-033 figure 14. output impe dance vs. frequency
AD8432 rev. 0 | page 9 of 28 0.1 1 10 100 frequency (mhz) 0.1 1 10 100 output impedance (k ? ) 08341-034 figure 15. output impedance vs . frequency in disable mode 0.1 1 10 1 10 100 1000 input-referred voltage noise (nv/ hz) f = 1mhz source resistance ( ? ) r s thermal noise alone 08341-036 figure 16. input-referred voltage noise vs. source resistance (r s ) 1 10 100 1 10 100 1000 output-referred voltage noise (nv/ hz) f = 1mhz source resistance ( ? ) g = 12.04db g = 18.06db g = 21.58db 08341-035 g = 24.08db figure 17. output-referred voltage noise vs. source resistance (r s ) 0.70 0.75 0.80 0.85 0.90 0.95 1.00 ?50 ?30 ?10 10 30 50 70 90 input voltage noise (nv/ hz) temperature (c) 08341-037 figure 18. input voltage noise vs. temperature 2 4 6 8 10 12 14 16 ?50 ?30 ?10 10 30 50 70 90 output voltage noise (nv/ hz) temperature (c) g = 12.04db g = 18.06db g = 21.58db g = 24.08db 08341-038 figure 19. output voltage noise vs. temperature 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0.01 0.1 1 10 100 input voltage noise (nv/ hz) frequency (mhz) 08341-221 g = 24.08db g = 21.58db g = 18.06db g = 12.04db figure 20. input voltage noise vs. frequency
AD8432 rev. 0 | page 10 of 28 0 2 4 6 8 10 12 14 16 18 20 0.01 0.1 1 10 100 output vol t age noise (nv/ hz) frequency (mhz) 08341-222 g = 24.08db g = 21.58db g = 18.06db g = 12.04db figure 21. output voltage noise vs. frequency ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1 10 100 imd3 (dbc) frequency (mhz) low tone high tone 08341-223 figure 22. imd3 vs. frequency 0 5 10 15 20 25 30 35 40 45 50 1 10 100 oip3 (dbm) g = 24.08db g = 12.04db frequency (mhz) 08341-224 figure 23. output third-outpu t intercept vs. frequency ?110 ?100 ?90 ?80 ?70 ?60 ?50 ? 40 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 distortion (dbc) v out (v p-p) hd2, 10mhz hd2, 1mhz hd3, 10mhz hd3, 1mhz measurement limit 08341-225 figure 24. harmonic distortion vs. differential output voltage, g = 12.04 db 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ? 40 distortion (dbc) v out (v p-p) hd2, 10mhz hd2, 1mhz hd3, 10mhz hd3, 1mhz measurement limit 08341-226 figure 25. harmonic distortion vs. differential output voltage, g = 24.08 db ?110 ?100 ?90 ?80 ?70 ?60 ? 50 0 5 10 15 20 25 distortion (dbc) c l (pf) 08341-227 hd2, 10mhz, 2v p-p hd2, 10mhz, 1v p-p hd3, 10mhz, 2v p-p hd3, 10mhz, 1v p-p hd2, 1mhz, 1v p-p hd2, 1mhz, 2v p-p hd3, 1mhz, 2v p-p hd3, 1mhz, 1v p-p figure 26. harmonic distortion vs. capacitive load (c l ), g = 12.04 db
AD8432 rev. 0 | page 11 of 28 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ? 40 0 5 10 15 20 25 30 35 distortion (dbc) c l (pf) 08341-228 hd2, 10mhz, 2v p-p hd2, 10mhz, 1v p-p hd3, 10mhz, 2v p-p hd3, 10mhz, 1v p-p hd2, 1mhz, 1v p-p hd2, 1mhz, 2v p-p hd3, 1mhz, 2v p-p hd3, 1mhz, 1v p-p figure 27. harmonic distortion vs. capacitive load (c l ), g = 24.08 db ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ? 50 0 200 400 600 800 1000 1200 1400 1600 1800 2000 distortion (dbc) r l ( ? ) 08341-229 hd2, 10mhz, 2v p-p hd2, 10mhz, 1v p-p hd3, 10mhz, 2v p-p hd3, 10mhz, 1v p-p hd2, 1mhz, 1v p-p hd2, 1mhz, 2v p-p hd3, 1mhz, 2v p-p hd3, 1mhz, 1v p-p figure 28. harmonic distortion vs. resistive load (r l ), g = 12.04 db ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ? 50 0 200 400 600 800 1000 1200 1400 1600 1800 2000 distortion (dbc) r l ( ? ) hd2, 10mhz, 2v p-p hd2, 10mhz, 1v p-p hd3, 10mhz, 2v p-p hd3, 10mhz, 1v p-p hd2, 1mhz, 1v p-p hd2, 1mhz, 2v p-p hd3, 1mhz, 2v p-p hd3, 1mhz, 1v p-p 08341-230 figure 29. harmonic distortion vs. resistive load (r l ), g = 24.08 db ?110 ?100 ?90 ?80 ?70 ?60 ? 50 2 4 6 8 10 12 14 16 18 distortion (dbc) gain (v/v) hd2, 10mhz, 2v p-p hd2, 1mhz, 1v p-p hd3, 10mhz, 1v p-p hd3, 1mhz, 2v p-p hd3, 1mhz, 1v p-p hd2, 10mhz, 1v p-p hd3, 10mhz, 2v p-p hd2, 1mhz, 2v p-p 08341-231 figure 30. harmonic distortion vs. gain ?120 ?115 ?110 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ? 70 0.1 1 10 100 crosstalk (db) frequency (mhz) 08341-232 figure 31. channel crosstalk vs. frequency 1v/di v 08341-132 100ns/div figure 32. overdrive re covery, g = 12.04 db
AD8432 rev. 0 | page 12 of 28 1v/di v 08341-013 100ns/div figure 33. overdrive re covery, g = 24.08 db 200mv/di v 10ns/div g = 12.04db g = 18.06db g = 21.58db g = 24.08db 08341-014 figure 34. small signal transient response vs. gain, v in = 100 mv p-p 100mv/di v 10ns/div 08341-015 figure 35. small signal transient response, g = 12.04 db 50mv/di v 10ns/div c l = 15pf c l = 10pf c l = 5pf 08341-016 figure 36. small signal transient response vs. capacitive load (c l ), g = 12.04 db 50mv/di v 10ns/div c l = 5pf c l = 10pf c l = 15pf c l = 20pf c l = 30pf 08341-017 figure 37. small signal transient response vs. capacitive load (c l ), g = 24.08 db 50mv/di v 10ns/div r l = 499 ? r l = 249 ? r l = 24.9 ? r l = 15 ? r l = 10 ? 08341-018 figure 38. small signal transient response vs. resistive load (r l ), g = 12.04 db
AD8432 rev. 0 | page 13 of 28 50mv/di v 10ns/div r l = 499 ? r l = 249 ? r l = 24.9 ? r l = 15 ? r l = 10 ? 08341-019 figure 39. small signal transient response vs. resistive load (r l ), g = 24.08 db 50mv/di v 10ns/div g = 12.04db g = 18.06db g = 21.58db g = 24.08db 08341-020 figure 40. small signal transient response vs. gain, v out = 200 mv p-p 500mv/di v 10ns/div g = 12.04db g = 21.58db g = 18.06db 08341-021 g = 24.08db figure 41. large signal transient response vs. gain, v in = 125 mv p-p 500mv/di v 10ns/div c l = 20pf c l = 15pf c l = 10pf c l = 5pf 08341-022 figure 42. large signal transient response vs. capacitive load (c l ), g = 12.04 db 500mv/di v 10ns/div c l = 30pf c l = 20pf c l = 15pf c l = 10pf c l = 5pf 08341-023 figure 43. large signal transient response vs. capacitive load (c l ), g = 24.08 db 500mv/di v 10ns/div r l = 499 ? r l = 249 ? r l = 24.9 ? r l = 15 ? 08341-024 figure 44. large signal transient response vs. resistive load (r l ), g = 12.04 db
AD8432 rev. 0 | page 14 of 28 500mv/di v 10ns/div r l = 499 ? r l = 249 ? r l = 24.9 ? r l = 15 ? r l = 10 ? 08341-025 figure 45. large signal transient response vs. resistive load (r l ), g = 24.08 db 500mv/di v 10ns/div g = 12.04db g = 21.58db g = 24.08db 0 8341-026 g = 18.06db figure 46. large signal transient response vs. gain, v out = 2 v p-p ?100 ?90 ?80 ?70 ?60 ?50 ?40 ? 20 ?30 0.01 0.1 1 10 100 psrr (db) frequency (mhz) g = 24.08db no bypass caps 08341-248 figure 47. psrr vs. frequency 20 22 24 26 28 30 ?60 ?40 ?20 0 20 40 60 80 100 supply current (ma) temperature (c) 08341-027 figure 48. supply current vs. temperature 0 20 40 60 80 100 120 140 ?60 ?40 ?20 0 20 40 60 80 100 supply cu r rent (a) temperature (c) 08341-028 figure 49. supply current vs. temperature in disable mode
AD8432 rev. 0 | page 15 of 28 08341-252 time (100s/div) 2 1 enb 5v/div output 50mv/div figure 50. small signal enable response 08341-251 time (100s/div) 2 1 enb 5v/div output 500mv/div figure 51. large signal enable response
AD8432 rev. 0 | page 16 of 28 test circuits r sh c sh r fb 0.1 f 0.1f 0.1f 0.1f 0.1f 1mhz (10mhz) 1mhz (10mhz lpf) opl spectrum analzyer r l r l ad8130 g = 1 475 ? 08341-046 56.2 ? dual filter hp lp 50? 1.7mhz (10.7mhz) 50 ? inh inl AD8432 lna1 inh inl figure 52. harmonic distortion vs. resistive load (r l ) measurements 08341-049 dual filter 1.7mhz (10.7mhz) r sh c sh r fb 0.1 f 0.1f 0.1f 0.1f 1mhz (10mhz) 1mhz (10mhz lpf) opl oph r l 0.1f 487 ? 487 ? 26.1 ? 1:1 26.1 ? c l c l lp hp in 50 ? 50 ? spectrum analyzer AD8432 lna1 inh inl figure 53. harmonic distortion vs. capacitive load (c l ) measurements 08341-047 r sh c sh r fb 0.1f 0.1f inh opl oph inl 0.1f 0.1f 0.1f 499 ? 5pf 499 ? 5pf diff probe networ k analyzer in out 50 ? 50 ? AD8432 lna1 figure 54. frequency response measurements 08341-048 0.1f 0.1f opl oph 0.1f 0.1f ad8129 g = 10 1k ? 50 ? 1k? spectrum analyzer AD8432 lna1 inh inl figure 55. voltage noise measurements
AD8432 rev. 0 | page 17 of 28 08341-050 diff probe r sh r fb c sh 0.1f 0.1f 0.1f 0.1f 0.1f 499 ? 5pf 499 ? 5pf x y 1mhz multiplier ch1 10mhz oscilloscope inh inl AD8432 lna1 figure 56. overdrive recovery measurements 08341-051 50 ? 0.1f inh opl oph 0.1f inl 0.1f 499 ? 5pf 0.1f 5pf 499 ? network analyzer out 0.1f r sh c sh r fb AD8432 lna1 figure 57. input impedance vs. frequency measurements 08341-052 50 ? 0.1 f inh opl oph 0.1f inl 0.1f 499 ? 0.1f network analyzer 0.1f r sh c sh r fb ad8130 lna1 figure 58. output impedance vs. frequency measurements 08341-054 0.1f 0.1f opl1 oph1 inh1 inl1 0.1f 0.1f ad8129 g = 10 1k ? 50 ? 1k? ?in +in out spectrum analyzer 0.1f r fb r s AD8432 lna1 figure 59. noise figure measurements
AD8432 rev. 0 | page 18 of 28 theory of operation low noise amplifier (lna) the AD8432 is a dual-channel, ultralow noise amplifier with integrated pin-strappable, gain-setting resistors. the resistors can be externally connected to achieve differential gains of 12.04 db, 18.06 db, 21.58 db, and 24.08 db (4, 8, 12, and 16). a simplified schematic of a lna is shown in figure 60 . the lna is driven with a single-ended input and measured differentially at the output. the inverting input inl must be ac-coupled to ground through a capacitor for proper operation. the lna cannot be driven differentially due to the asymmetry of the internal gain setting resistors. the gain from the inverting input inl to the single-ended output (oph or opl) does not match the gain from the noninverting input inh to the single- ended output. the AD8432 inputs have a dc bias voltage of 3.25 v, which is generated internally. the inputs must be ac-coupled through a series capacitor to maintain the dc bias level of the inputs. likewise, the AD8432 outputs have a dc bias voltage of 2.5v. an ac coupling capacitor in series with each connection is recommended to prevent improper loading of the outputs. the AD8432 supports a differential output voltage of 4.8 v p-p for the common-mode output voltage of 2.5 v. therefore, for a differential gain g = 12.04 db, the maximum input voltage allowed is 1.2 v p-p. clamping the inputs ensures quick recovery from large input voltages. the input back-to-back diodes, which are integrated inside the die (ind1 and ind2), should be used for the lowest gain configuration (12.04 db) to protect the input from overdriving. they should be connected after the source resistance or before the inh coupling capacitor. the use of a fully differential topology and negative feedback minimizes distortion. a differential signal enables smaller swings at each output, which results in reduction of third-order distortion. the AD8432 is a voltage feedback amplifier. due to gain band- width product (gbw), a decrease in bandwidth should be expected as the gain increases. table 5 displays the values of ?3 db bandwidth for each gain with unterminated input impedance. gain setting technique pin strapping is used to set the gain of the amplifier. gain setting resistors are integrated in the lna and are accessible externally through the goh, gmh, gml, and gol pins. by externally shorting these pins, and thereby shorting or connecting the internal resistors, the AD8432 can be configured for four different gains. tabl e 5 shows which pins must be connected to achieve the desired gain. rg2 12 ? rg3 24? rg4 48? rg7 48? rg6 24 ? rg5 24 ? rg1 12? i i i i cinh inh oph vps opl inl r fb c fb q2 q1 gmh goh gml gol cinl gnd gnd gnd rsh rs csh vs 08341-039 figure 60. simplified schematic of lna table 5. gain setting using pin-strapping technique and 3 db bandwidth for each gain configuration differential gain (db) single gain (db) ?3 db bw (mhz) rg1 () rg2 () rg3 () rg4 () rg5 () rg6 () rg7 () 12.04 6.02 200 12 12 connect gmh to goh connect goh to oph 24 connect gml to gol connect gol to opl 18.06 12.04 90 12 12 24 connect goh to oph 24 24 connect gol to opl 21.58 15.56 50 12 12 connect gmh to goh 48 24 connect gml to gol 48 24.08 18.06 32 12 12 24 48 24 24 48
AD8432 rev. 0 | page 19 of 28 the single-ended gain from inh to oph (see figure 60 ) is defined as g1 g4g3g2g1 inhoph r rrrr g +++ = ? the single-ended gain from inh to opl is defined as g1 g7 g6g5 inhopl r rrr g ++ ?= ? the values of the seven gain resistors were chosen so that both single-ended gains are equal. for example, to set a gain of 12.04 db (g = 4) differentially, the gain from inh to each output (oph, opl) should be 6.02 db (g = 2). inh to oph: for r g1 = r g2 = r g , then 2 2 = = + = ? g g g1 g2g1 inhoph r r r rr g inh to opl: for r g1 = r g and r g5 = 2 r g , then 2 2 ?= ?=?= ? g g g1 g5 inhopl r r r r g active input resistance matching the AD8432 reduces noise and optimizes signal power transfer by using active input termination to perform signal source resistance matching. the primary purpose of input impedance matching is to optimize the input signal power transfer. with resistive termination, the input noise increases due to the thermal noise of the terminating resistor and the increased contribution of the input voltage noise generator of the lna. with active impedance matching, however, the contributions of both are smaller than they would be for resistive termination by a factor of 1/(1 + ?lna gain). the noise figure (nf) for the three terminating schemes are shown in figure 62 . lna r in v in v out r s inh unterminated lna r in v in v out r s r s inh resistive termination lna r in v in v out r s r fb inh active impedance match 08341-009 figure 61. input resistance matching to achieve this active impedance match, connect a feedback resistor r fb between the inh and opl (see figure 61 ). r in is given in equation 1, where g/2 is the single-ended gain. 2 1 g r r fb in + = (1) in addition, to further reduce the input resistance, there is an internal resistance of 6.2 k in parallel with the source resistance, such that internal fb in r g r r 2 1 + = (2) equation 3 should be used to calculate r fb accurately for a desired input resistance and single-ended gain. refer to tabl e 6 for calculated results for r fb for several input resistance and gain combinations. k 2.6 , 1 2 1 = ? ? ? ? ? ? ? + =? internal internal in in fb r r r g r r (3) 08341-267 0 1 2 3 4 5 6 7 8 100 50 1000 noise figure (db) r s ( ) (simulated results) active impedance match unterminated resistive termination (r s = r in ) figure 62. noise figure vs. r s for resistive, active match, and unterminated inputs 08341-268 0 2 6 4 8 10 12 14 16 18 100 50 1k noise figure (db) r s ( ) (simulated results) r in = unterminated r in = 50 r in = 75 r in = 100 r in = 200 r in = 1k figure 63. noise figure vs. r s for various values of r in , actively matched
AD8432 rev. 0 | page 20 of 28 the user must determine the level of matching accuracy desired and adjust r fb accordingly. the r fb and c fb network presents a load to opl that oph does not see. the user may add an identical load on oph, to improve slightly the distortion caused by this imbalance. there is a feedback capacitor (c fb ) in series with r fb (see figure 60 ) because the dc levels of the positive output and the positive input are different. at higher frequencies, the value of the feedback capacitor needs to be considered. the unterminated bandwidth (r fb = ) is 200 mhz. the AD8432 has a low input referred voltage noise of 0.85 nv/hz at the lowest gain, 12.04 db (unterminated configuration). to achieve such low noise, the dual amplifier consumes 24 ma, resulting in a power consumption of 120 mw. table 6. feedback resistance for several r in and gain combinations desired r in () differential gain (v/v) single-ended gain, g/2 (v/v) exact r fb (), equation 2 r fb (), 1% standard value actual r in (), equation 2 50 4 2 151.2 150 49.6 75 4 2 227.8 226 74.4 100 4 2 304.9 301 98.7 200 4 2 620 619 199.7 1 k 4 2 3.58 k 3.57 k 998.4 50 8 4 252 250 49.6 100 8 4 508.2 511 100.5 50 12 6 352.9 357 50.6 100 12 6 711.5 715 100.5 50 16 8 453.7 453 49.9 100 16 8 914.8 909 99.4
AD8432 rev. 0 | page 21 of 28 applications information the AD8432 lna provides precision gain and ultralow noise performance with minimal external components. because it is a high performance part, care must be taken to ensure that it is configured optimally to attain the best performance and dynamic range for the system. typical setup the internal bias circuitry of the AD8432 sets the input bias voltage at 3.25 v and the output bias voltage at 2.5 v. it is important to ac-couple the inputs through a capacitor to maintain the internal dc bias levels. when active input termination is used (r fb ), a decoupling capacitor (c fb ) is required to isolate the input and output bias voltages of the lna. a typical value for c fb is 0.1 f, but a smaller value capacitor is more appropriate at higher frequencies. the unterminated input impedance of the AD8432 is 6.2 k. any input resistance between 50 and 6.2 k can be synthesized using active impedance matching. at the lowest gain (12.04 db), the gain response exhibits some peaking at higher frequencies. an rc shunt network at the input (see r shx and c shx in figure 64 ) is recommended to reduce gain peaking and enhance stability at higher frequencies. table 7 shows the recommended values of r fb , c sh , and r sh for all four gains and several input impedance combinations. the values for the c sh and r sh network are determined empirically and can be customized as needed to optimize performance. as r in increases, the value of c sh diminishes, and for higher input impedance values, no capacitor may be required. 08341-040 r l r sh2 15 ? c sh2 47pf c l out2+ out2? lna2 0.1f 0.1f 0.1f 0.1f fb 120nh in2 inl2 ind2 inh2 oph2 opl2 gmh2 goh2 gol2 gml2 r fb2 c fb2 0.1f c fb1 0.1f AD8432 r l r sh1 15 ? c sh1 47pf c l out1+ out1? lna1 bias 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f fb 120nh in1 inl1 ind1 inh1 oph1 opl1 gmh1 goh1 gol1 gml1 fb 120nh r fb1 g = 12db comm vps2 vps1 enb figure 64. typical AD8432 setup, g = 12.04 db
AD8432 rev. 0 | page 22 of 28 table 7. external components selections for common input impedance r in () gain (db) r fb () c sh (pf) r sh () ?3 db bw (mhz) 50 12 150 47 15 176 18 249 30 15 116 21 357 none none 117 24 453 none none 87 75 12 226 36 15 167 18 383 none none 144 21 536 none none 100 24 681 none none 72 100 12 301 30 15 164 18 511 none none 134 21 715 none none 90 24 909 none none 63 200 12 619 18 15 164 18 1.02 k none none 116 21 1.43 k none none 74 24 1.87 k none none 51 1 k 12 3.57 k 10 10 160 18 5.9 k none none 99 21 8.25 k none none 61 24 10.7 k none none 43 unterminated, r s = 50 12 none none 178 18 none none 95 21 none none 59 24 none none 40 unterminated, r s = 0 12 none none 210 18 none none 96 21 none none 55 24 none none 38
AD8432 rev. 0 | page 23 of 28 i/q demodulation front end the AD8432 low noise amplifiers can be used to drive the differential rf inputs of the dual ad8333 or the quad ad8339 i/q demodulators. the primary application for the ad8339 is phased array beamforming in medical ultrasound, specifically in cw doppler processing. other applications include phased array radar and smart antennas for mobile communications. 08341-041 ad8021 a d8021 20 ? 787 ? 787? 2.2nf 2.2nf rf1n rf1p i1op q1op 4lop 20 ? 0.1f 0.1f 0.1f AD8432 ad8339 q1 i1 figure 65. block diagram of AD8432 + ad8339 application for ultrasound beamforming because of its low output noise and low distortion, the AD8432 ensures minimal degradation in dynamic range while amplifying the rf input signal. at the lowest gain of 12.04 db, the AD8432 contributes only 3.4 nv/hz output voltage noise. figure 65 shows a simplified block diagram of one channel of the AD8432 driving the ad8339 . the AD8432 outputs can be connected directly to the ad8339 rf inputs through 20 resistors. the 4lop and 4lon pins of the ad8339 are driven by a differential clock signal, which has a frequency 4 that of the rf inputs. the ad8339 downconverts the rf signals, generates quadrature, and phase-shifts the resultant i and q signals. the i and q outputs of the ad8339 are current outputs. a transimpedance amplifier, such as the ad8021 , processes the outputs and performs several functions, including the following: x current-to-voltage conversion x summation amplifier for multiple channels x active low-pass filter in beamforming applications, the i and q outputs of a number of receiver channels are summed, which increases the system dynamic range by 10 log 10 (n), n being the number of channels being summed. the external rc feedback network of the ad8021 is a 100 khz low-pass filter as shown in figure 65 . refer to the ad8333 and ad8339 datasheets for more details on implementing i/q demodulators. evaluation boards are available for the AD8432 and the ad8339 to facilitate system level design and test. a detailed reference schematic of the setup is shown in figure 66 . the AD8432 is shown in this configuration with a gain of 12.04 db, with unterminated inputs. if active termination is preferred, use an r fb and c fb network as discussed in the theory of operation . clamping diodes ind1/ind2 can be connected to in1/in2 to protect the lna input from being overdriven. 08341-043 bias AD8432 inl2 ind2 inh2 inl1 ind1 inh1 enb vps1 vps2 comm oph2 lna1 lna2 in2 in1 0.1f ad8339 rf1p rf1n 20 ? 20 ? 20 ? 20 ? rf2p rf2n q1 + q2 787? 0 ? 27 3 4 6 + ? q1op ad8021 vpos vneg 4lop r sh1 15? g = 12db g = ?1.3db lpf f c = 100khz 4lo c sh1 47 pf r sh2 15? c sh2 47 pf 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f opl2 oph1 opl1 gmh2 goh2 gol2 gml2 gmh1 goh1 gol1 gml1 ? 5v ? 5v +5v 0.1f 0.1f +5v i1op q2op i2op 2.2nf i1 + i2 787 ? 0 ? 27 3 4 6 + ? ad8021 ? 5v 0.1f 0.1f +5v 2.2nf figure 66. schematic of AD8432 (g = 12.04 db) + ad8339 application for ultrasound beamforming
AD8432 rev. 0 | page 24 of 28 differential-to-single -ended conversion some applications require the low noise and high dynamic range of the AD8432; however, they may also require a single- ended output, rather than a differential output. the ad8129 and ad8130 differential receiver amplifier can be used for the differential-to-single-ended conversion of the AD8432 output, as shown in figure 67 . the ad8129 is a low noise, high gain (10 or greater) amplifier intended for applications over very long cables, where signal attenuation is significant. the ad8130 is stable at a gain of 1 and can be used for applications where lower gains are required. the ad8129 and ad8130 have user-adjustable gain, set by the ratio of two resistors, to help compensate for losses in the transmission line. a transformer or balun can also be used to convert the differential output of the AD8432 to a single-ended output. transformers have lower distortion; however, care must be taken to properly match the impedance of the transformer. the test circuit for distortion measurements in figure 53 uses an adtt1-1 transformer to perform differential-to-single-ended conversion. 08341-044 ? ? + + 1 8 4 5 6 7 2 ?v s +v s v out1 bias inl1 ind1 inh1 enb vps1 vps2 comm oph1 opl1 lna1 in1 20 ? 499 ? 499 ? 20 ? r sh1 15? c sh1 47 pf 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f gmh1 goh1 gol1 gml1 series r if driving high cap load ac-coupling caps (AD8432 has 2.5v output bias) ad8130 r?s provide bias current path and termination if necessary g = 12 db figure 67. AD8432 differential-to-single-ended conversion using the ad8129/ad8130 with unity gain
AD8432 rev. 0 | page 25 of 28 evaluation board figure 68 shows the AD8432 evaluation board, and the schematic diagram is shown in figure 69 . using the board is a convenient and fast way to verify system design and assess the performance of the AD8432 under the user-specific operating conditions. the board provides access to all lna inputs, outputs, and gain setting pins. the board is shipped in a typical g = 12.04 db configuration but is designed to allow customization of the setup as required. the AD8432-evalz requires a single 5 v power supply. an on-board switch (s1) allows vps to drive the enable (enb) input. gain setting headers (w5 to w12) are provided across the gain setting pins and can be shorted using jumpers to allow gain setting quickly and easily. alternately, it is recommended to short the gain setting pins using surface-mount (0402), 0 resistors (r1 to r4, r9 to r12) that eliminate the small parasitic capacitances from longer trace lengths to the headers. as shipped, the evaluation board is configured for g = 12.04 db with these 0 resistors. table 8 outlines which resistors or headers need to be installed or shorted for each gain configuration. table 8. gain setting using resistors or headers gain (v/v) lna1 lna2 4 8 12 16 r1 w5 r9 w9 x 1 x 1 r2 w6 r10 w10 x 1 x 1 r3 w7 r11 w11 x 1 x 1 r4 w8 r12 w12 x 1 x 1 1 x = shorting the indicated header or resistor. 08341-045 figure 68. evaluation board
AD8432 rev. 0 | page 26 of 28 schematic 08341-042 enb vps1 oph1 goh1 gmh1 gml1 ind2 vps2 oph2 goh2 gmh2 gml2 gol1 opl1 com1 com2 opl2 gol2 inh1 inl1 ind1 comm inl2 inh2 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 AD8432 eval board schematic test point oph1 oph2 opl2 opl1 gnd1 in1 in2 prb1 w1 comm inl2 prb2 inh2 l1 120nh fb c5 0.1f c1 0.1f c2 0.1f c sh 2 47pf r sh2 15 ? c6 0.1f c4 0.1f vps2 gnd2 gnd3 w2 r sh1 15 ? c sh1 47pf inh1 opl2 gol1 opl1 com1 inl1 prb4 c12 0.1f dni c11 0.1f dni cl4 dni cl3 dni c13 0.1f dni c14 0.1f dni rl4 dni rl3 dni r14 dni t2 3 14 6 2 r16 453 ? dni r15 453 ? dni r18 0 ? dni vout2 prb3 c7 0.1f dni c8 0.1f dni cl1 dni cl2 dni c10 0.1f dni c9 0.1f dni rl1 dni rl2 dni r5 dni t1 3 14 6 2 r7 453 ? dni r4 0 ? r3 0 ? r2 0 ? r1 0 ? w8 w12 r8 453 ? dni r17 0 ? dni vout1 r6 dni r13 dni gol2 pin 0 exposed paddle (tied to gnd) AD8432 top view (not to scale) r12 0 ? gnd4 gnd5 gnd6 gnd gnd w3 vpos vpos vps1 +5v oph1 enb enable disable s1 goh1 gmh1 gml1 w5 w6 w7 banan a jack banan a jack vpos oph2 r fb 1 dni c fb 1 0.1f dni c3 0.1f l3 120nh fb l4 120nh fb l2 120nh fb r fb 2 dni c fb 2 0.1f dni r11 0 ? r10 0 ? r9 0 ? goh2 gmh2 gml2 w9 w10 w11 w4 pin 1 identifier figure 69. schematic
AD8432 rev. 0 | page 27 of 28 power supply the AD8432 should be powered by a single 5 v supply connected to the vpos terminal. separate supplies can be used for vps1, vps2, and enb, or they can all be tied to vpos by shorting the w3 and w4 headers and the s1 switch. ferrite beads and decoupling capacitors are installed for isolation, protection, and power supply noise reduction. input termination active input impedance matching can be realized by installing a feedback resistor (r fb ), the value of which is determined by the gain and source impedance, as described in the theory of operation section. c fb provides the necessary ac coupling between the input and output when using active termination; a 0.1 f capacitor value is recommended. the r fb and c fb network presents a load to opl, and an equivalent load at oph can be used to balance the differential output. input clamping diodes (ind1 and ind2) can be connected to the inputs, by shorting the connection on the w1 and w2 headers. the diodes provide overvoltage protection to the input and enable faster overdrive recovery times, especially at the lowest gain (12.04 db). output the AD8432 evaluation board provides the space to configure the output loading conditions required by the user, by populating the given footprints (for example, rl1, rl2, c7, and c8). sma connectors are available at the outputs, and space for a transformer is also available for differential-to-single-ended conversion. the 4-pin headers, prb3 and prb4, are placed close to the AD8432, and they provide a way for monitoring the differential output or the single-ended output using a high impedance differential probe. the two inner pins of the headers are connected to opl/oph, and the two outer pins of the headers are connected to ground. there are several footprints provided to install ac coupling capacitors at the outputs (c7 to c14). the AD8432 outputs are biased internally at 2.5 v. to maintain the dc bias level, use coupling capacitors between the outputs and the load.
AD8432 rev. 0 | page 28 of 28 outline dimensions 0.50 bsc 0.50 0.40 0.30 0.30 0.25 0.18 compliant to jedec standards mo-220-wggd. 112108-a bottom view top view exposed pad p i n 1 i n d i c a t o r 4.10 4.00 sq 3.90 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indi c ator 1 24 7 12 13 18 19 6 2.65 2.50 sq 2.45 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 70. 24-lead lead frame chip scale package [lfscp_wq] 4 mm 4 mm, very very thin quad (cp-24-7) dimensions shown in millimeters ordering guide model temperature range packag e description package option AD8432acpz-r7 1 ?40c to +85c 24-lead lfcsp_wq, 7 tape and reel cp-24-7 AD8432acpz-rl 1 ?40c to +85c 24-lead lfcsp_wq, 13 tape and reel cp-24-7 AD8432acpz-wp 1 ?40c to +85c 24-lead lfcsp_wq, waffle pack cp-24-7 AD8432-evalz 1 evaluation board 1 z = rohs compliant part. ?2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d08341-0-10/09(0)

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